FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

I/O Base Address Configuration Register

TABLE 73 - I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION

LOGICAL

BASE I/O

DEVICE LOGICAL REGISTER

NUMBER DEVICE

INDEX

RANGE

(NOTE3)

FIXED

BASE OFFSETS

0x00

FDC

(Note 4)

0x60,0x61

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES

+0 : SRA

+1 : SRB

+2 : DOR

+3 : TSR

+4 : MSR/DSR

+5 : FIFO

+7 : DIR/CCR

0x03

Parallel

Port

0x60,0x61

[0x100:0x0FFC]

ON 4 BYTE BOUNDARIES

(EPP Not supported)

or

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES

(all modes supported,

EPP is only available when

the base address is on an

8-byte boundary)

+0 : Data|ecpAfifo

+1 : Status

+2 : Control

+3 : EPP Address

+4 : EPP Data 0

+5 : EPP Data 1

+6 : EPP Data 2

+7 : EPP Data 3

+400h : cfifo|ecpDfifo|tfifo

|cnfgA

+401h : cnfgB

+402h : ecr

0x04

Serial Port

1

0x60,0x61

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES

+0 : RB/TB|LSB div

+1 : IER|MSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

0x05

Serial Port

2

0x60,0x61

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES

+0 : RB/TB|LSB div

+1 : IER|MSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LSR

+6 : MSR

+7 : SCR

182

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