TABLE 79 - UART INTERRUPT OPERATION
UART1
UART2
IRQ PINS
UART1
UART1
UART2
UART2 Share IRQ UART1 UART2
OUT2 bit IRQ State OUT2 bit IRQ State
Bit
Pin State Pin State
This part of the table is based on the assumption that both UARTS have selected different
IRQ pins
0
Z
0
Z
0
Z
Z
1
asserted
0
Z
0
1
Z
1
de-asserted 0
Z
0
0
Z
0
Z
1
asserted
0
Z
1
0
Z
1
de-asserted 0
Z
0
1
asserted
1
asserted
0
1
1
1
asserted
1
de-asserted 0
1
0
1
de-asserted 1
asserted
0
0
1
1
de-asserted 1
de-asserted 0
0
0
0
Z
0
Z
1
Z
Z
1
asserted
0
Z
1
1
1
1
de-asserted 0
Z
1
0
0
0
Z
1
asserted
1
1
1
0
Z
1
de-asserted 1
0
0
1
asserted
1
asserted
1
1
1
1
asserted
1
de-asserted 1
1
1
1
de-asserted 1
asserted
1
1
1
1
de-asserted 1
de-asserted 1
0
0
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ
number. However, if they are set to the same number then no damage to the chip will result.
191