FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

NAME

Soft Power Status

Register 2

Default = 0x00

on Vbat POR

REG

INDEX

0xB3 R/W

DEFINITION

The following bits are the status for the wake-up

function of the nPowerOn bit. These indicate

which of the enabled wakeup functions caused the

power up.

STATE

C

1 = Occured

0 = Did not occur since last cleared

The following signals are latched to detect and

hold the soft power event (Type 1) (Note 1)

Bit[0] RXD1: UART 1 Receive Data; high to low

transition on the pin, cleared by a read of this

register

Bit[1] RXD2: UART 2 Receive Data; high to low

transition on the pin, cleared by a read of this

register

Bit[3] RING Status bit “RING_STS”; Latched,

cleared on read.

0= nRING input did not occur.

1= Ring indicator input occurred on the nRING pin

and, if enabled, caused the wakeup (activated

nPowerOn)

Bit[4] Reserved

Bit[5] CIR Status bit “CIR_STS”; latched, cleared

on read.

0= CIR wakeup event did not occur.

1= CIR wakeup event occurred and, if enabled,

caused the wakeup (activated nPowerOn).

The following signal is latched to detect and hold

the soft power event (Type 3) (Note 1) but the

output of the latch does not feed into the power

down circuitry:

Bit[2] Button: Button pressed, Cleared by a read of

this register

Bits[7:6] Reserved

198

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