FDC37B78X 查看數據表（PDF） - SMSC -> Microchip
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FDC37B78X
SMSC -> Microchip
FDC37B78X Datasheet PDF : 258 Pages
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TABLE 102 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING
NAME
DESCRIPTION
MIN TYP MAX
t1 nIOW Asserted to PDATA Valid
0
50
t2 nWAIT Asserted to nWRITE Change (Note 1)
60
185
t3 nWRITE to Command Asserted
5
35
t4 nWAIT Deasserted to Command Deasserted
60
190
(Note 1)
t5 nWAIT Asserted to PDATA Invalid (Note 1)
0
t6 Time Out
10
12
t7 Command Deasserted to nWAIT Asserted
0
t8 SDATA Valid to nIOW Asserted
10
t9 nIOW Deasserted to DATA Invalid
0
t10 nIOW Asserted to IOCHRDY Asserted
0
24
t11 nWAIT Deasserted to IOCHRDY Deasserted
60
160
(Note 1)
t12 IOCHRDY Deasserted to nIOW Deasserted
10
t13 nIOW Asserted to nWRITE Asserted
0
70
t14 nWAIT Asserted to Command Asserted (Note 1)
60
210
t15 Command Asserted to nWAIT Deasserted
0
10
t16 PDATA Valid to Command Asserted
10
t17 Ax Valid to nIOW Asserted
40
t18 nIOW Asserted to Ax Invalid
10
t19 nIOW Deasserted to nIOW or nIOR Asserted
40
t20 nWAIT Asserted to nWRITE Asserted (Note 1)
60
185
t21 nWAIT Asserted to PDIR Low
0
t22 PDIR Low to nWRITE Asserted
0
UNITS
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is
considered to have settled after it does not transition for a minimum of 50 nsec.
242
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