FDC37B78X 查看數據表（PDF） - SMSC -> Microchip
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FDC37B78X
SMSC -> Microchip
FDC37B78X Datasheet PDF : 258 Pages
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TABLE 105 - EPP 1.7 DAT OR ADDRESS READ CYCLE TIMING
NAME
DESCRIPTION
MIN TYP MAX
t2 nIOR Deasserted to Command Deasserted
50
t3 nWAIT Asserted to IOCHRDY Deasserted
0
40
t4 Command Deasserted to PDATA Hi-Z
0
t5 Command Asserted to PDATA Valid
0
t8 nIOR Asserted to IOCHRDY Asserted
24
t10 nWAIT Deasserted to IOCHRDY Deasserted
50
t11 IOCHRDY Deasserted to nIOR Deasserted
0
t12 nIOR Deasserted to SDATA High-Z (Hold Time)
0
40
t13 PDATA Valid to SDATA Valid
40
t15 Time Out
10
12
t19 Ax Valid to nIOR Asserted
40
t20 nIOR Deasserted to Ax Invalid
10
t21 Command Deasserted to nWAIT Deasserted
0
t22 nIOR Deasserted to nIOW or nIOR Asserted
40
t23 nIOR Asserted to Command Asserted
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
Note: WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an
EPP Read.
248
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