FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

FIFO

MODE

ONLY

BIT 3

0

0

0

1

0

0

TABLE 34 - INTERRUPT CONTROL

INTERRUPT

IDENTIFICATION

REGISTER

INTERRUPT SET AND RESET FUNCTIONS

PRIORIT INTERRUPT

BIT 2 BIT 1 BIT 0 Y LEVEL

TYPE

INTERRUPT

SOURCE

0

0

1

-

None

None

INTERRUPT

RESET

CONTROL

-

1

1

0 Highest Receiver Line Overrun Error, Reading the Line

Status

Parity Error,

Status Register

Framing Error or

Break Interrupt

1

0

0 Second Received Data Receiver Data Read Receiver

Available

Available

Buffer or the

FIFO drops below

the trigger level.

1

0

0 Second Character

Timeout

Indication

No Characters

Have Been

Removed From

or Input to the

RCVR FIFO

during the last 4

Char times and

there is at least 1

char in it during

this time

Reading the

Receiver Buffer

Register

0

1

0 Third

Transmitter

Holding

Register

Empty

Transmitter

Holding Register

Empty

Reading the IIR

Register (if

Source of

Interrupt) or

Writing the

Transmitter

Holding Register

0

0

0 Fourth MODEM

Status

Clear to Send or

Data Set Ready

or Ring Indicator

or Data Carrier

Detect

Reading the

MODEM Status

Register

74

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