FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

The bit map of the Extended Parallel Port registers is:

D7

D6

D5

D4

D3

D2

D1

D0

Note

data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ecpAFifo

Addr/RLE

Address or RLE field

2

dsr

nBusy

nAck

PError

Select

nFault

0

0

0

1

dcr

0

0

Direction ackIntEn SelectIn

nInit

autofd strobe

1

cFifo

Parallel Port Data FIFO

2

ecpDFifo

ECP Data FIFO

2

tFifo

Test FIFO

2

cnfgA

0

0

0

1

0

0

0

0

cnfgB

compress intrValue

Parallel Port IRQ

Parallel Port DMA

ecr

MODE

nErrIntrEn dmaEn serviceIntr

full

empty

Note 1: These registers are available in all modes.

Note 2: All FIFOs use one common 16 byte FIFO.

Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration

Registers.

ISA IMPLEMENTATION STANDARD

This specification describes the standard ISA

interface to the Extended Capabilities Port

(ECP). All ISA devices supporting ECP must

meet the requirements contained in this section

or the port will not be supported by Microsoft.

For a description of the ECP Protocol, please

refer to the IEEE 1284 Extended Capabilities

Port Protocol and ISA Interface Standard, Rev.

1.14, July 14, 1993. This document is available

from Microsoft.

Description

The port is software and hardware compatible

with existing parallel ports so that it may be

used as a standard LPT port if ECP is not

required. The port is designed to be simple and

requires a small number of gates to implement.

It does not do any "protocol" negotiation, rather

it provides an automatic high burst-bandwidth

channel that supports DMA for ECP in both the

forward and reverse directions.

Small FIFOs are employed in both forward and

reverse directions to smooth data flow and

improve the maximum bandwidth requirement.

The size of the FIFO is 16 bytes deep. The port

supports an automatic handshake for the

standard parallel port to improve compatibility

mode transfer speed.

The port also supports run length encoded

(RLE) decompression (required) in hardware.

Compression is accomplished by counting

identical bytes and transmitting an RLE byte

that indicates how many times the next byte is

to be repeated. Decompression simply

intercepts the RLE byte and repeats the

following byte the specified number of times.

Hardware support for compression is optional.

97

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