COM20022V-HT 查看數據表（PDF） - SMSC -> Microchip

零件编号

产品描述 (功能)

生产厂家

COM20022V-HT

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

TIME-OUT

MAX NODE

RCNTM1 RCNTM0

PERIOD

COUNT

0

0

210 mS

Up to 255 nodes

0

1

52.5 mS

Up to 64 nodes

1

0

26.25 mS

Up to 32 nodes

1

1

13.125 mS*

Up to 16 nodes*

Note*: The node ID value 255 must exist in the network for the 13.125 mS time-out to be valid.

BUS CONTROL REGISTER

The Bus Control Register is new to the

COM20022. It is an 8-bit read/write register

accessed when the Sub Address Bits SUBAD[2:0]

are set up accordingly (see the bit definitions of

the Sub Address Register). This register contains

bits for control of the DMA functionality. The

DRQPOL bit is used to set the active polarity of

the DREQ pin. The TCPOL bit is used to set the

active polarity of TC pin.

The DMAMD[0,1] bits select the data transfer

mode of the DMA, either non-burst, burst,

Programmable-Burst by timer or programmable

burst by cycle counter.

This transfer mode influences to the timing the

DREQ pin. The use of the ITCEN/RTRG bit

transfer mode dependent. ITCEN is the Internal

Terminal Counter Enable. It is used to select

whether the DMA is terminated by external TC or

by either internal or external TC. ITCEN is for

Non-Burst or Burst mode. RTRG selects the re-

trigger mode as either external or internal. It is

for the two Programmable-Burst modes. If

RTRG = 0, the deasserted DREQ pin is

reasserted on the falling edge of the nREFEX

pin. If RTRG = 1, the deasserted DREQ pin is

reasserted by the timeout of the internal timer

(350 ns or 750 ns, as selected by the GTTM bit.)

See Figure below.

RTRG=0

RTRG=1

nREFEX

DREQ

nDACK

nWR/nRD

DREQ

nDACK

nWR/nRD

350/750ns

FIGURE 12 - ILLUSTRATION OF THE EFFECT OF RTRG BIT ON DMA TIMING

34

Share Link: