COM20022V-HT 查看數據表（PDF） - SMSC -> Microchip

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COM20022V-HT

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

BIT

BIT NAME

7-0 Address 7-0

Table 8 - Address Pointer Low Register

SYMBOL

DESCRIPTION

A7-A0

These bits hold the lower 8 address bits which provide the

addresses to RAM.

SWAP

When 16 bit access is enabled, (W16=1), A0 becomes the

SWAP bit. Swap bit is undefined after a hardware reset.

The swap bit must be set before W16 bit is set to “1”. The

swap bit is used to swap the upper and lower data byte.

The swap bit influences both CPU cycle and DMA cycle.

See Table Below.

Detected Host

Interface Mode

Intel 80xx Mode

Swap Bit

0

D15-D8

Pin

Odd

D7-D0

Pin

Even

(RD, WR Mode)

1

Even

Odd

Motorola 68xx Mode

0

Even

Odd

(DIR, DS Mode)

1

Odd

Even

BIT

BIT NAME

7-3 Reserved

2,1,0 Sub Address 2,1,0

Table 9 - Sub Address Register

SYMBOL

DESCRIPTION

These bits are undefined.

SUBAD

2,1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD2

0

0

0

0

1

1

1

1

SUBAD1 SUBAD0 Register

0

0Tentative ID \ (Same

0

1Node ID

\ as in

1

0Setup 1 / Config

1

1Next ID / Register)

0

0Setup 2

0

1Bus Control

1

0DMA Count

1

1 Reserved

SUBAD1 and SUBAD0 are exactly the same as exist in the

Configuration Register. SUBAD2 is cleared automatically by

writing the Configuration Register.

40

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