Z8F041APJ020EG 查看數據表（PDF） - Zilog

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Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

103

– Set or clear CTSE to enable or disable control from the remote receiver using the

CTS pin

8. Execute an EI instruction to enable interrupts.

The UART is now configured for interrupt-driven data transmission. Because the UART

Transmit Data Register is empty, an interrupt is generated immediately. When the UART

Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the

following:

1. Write the UART Control 1 Register to select the multiprocessor bit for the byte to be

transmitted:

2. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if

sending a data byte.

3. Write the data byte to the UART Transmit Data Register. The transmitter automati-

cally transfers the data to the Transmit Shift Register and transmits the data.

4. Clear the UART Transmit interrupt bit in the applicable Interrupt Request Register.

5. Execute the IRET instruction to return from the interrupt-service routine and wait for

the Transmit Data Register to again become empty.

Receiving Data using the Polled Method

Observe the following steps to configure the UART for polled data reception:

1. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud

rate for the incoming data stream.

2. Enable the UART pin functions by configuring the associated GPIO port pins for

alternate function operation.

3. Write to the UART Control 1 Register to enable MULTIPROCESSOR Mode func-

tions, if appropriate.

4. Write to the UART Control 0 Register to:

– Set the receive enable bit (REN) to enable the UART for data reception

– Enable parity, if appropriate and if Multiprocessor mode is not enabled and select

either even or odd parity.

5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data

Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate

available data, continue to Step 5. If the Receive Data Register is empty (indicated by

a 0), continue to monitor the RDA bit awaiting reception of the valid data.

PS022827-1212

PRELIMINARY

Operation

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