OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Timing Characteristics (continued)

Table 46A. OR2CxxA/OR2TxxA Programmable I/O Cell Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Speed

-3

-4

-5

-6

-7

Unit

Min Max Min Max Min Max Min Max Min Max

S Inputs (TJ = 85 °C, VDD = min)

Input Rise Time

E Input Fall Time

Pad to In Delay

Pad to Nearest PFU Latch Output

IC Delay Added to General Routing

D (input buffer in delay mode for

OR2C/2T15A and smaller

devices)

V E Delay Added to General Routing

(input buffer in delay mode for

OR2C/2T26A and OR2C/2T40A)

E U Delay Added to Direct-FF Routing

(input buffer in delay mode for

OR2C/2T15A and smaller

D devices)

IN Delay Added to Direct-FF Routing

(input buffer in delay mode for

OR2C/2T26A and OR2C/2T40A)

TR

TF

PAD_IN_DEL

CHIP_LATCH

—

—

—

—

— 500 — 500 — 500 — 500 — 500 ns

— 500 — 500 — 500 — 500 — 500 ns

— 1.5 — 1.3 — 1.2 — 1.2 — 1.1 ns

— 4.7 — 4.1 — 3.5 — 3.1 — 2.9 ns

— 7.0 — 6.0 — 5.9 — 6.2 — 5.8 ns

— 9.7 — 8.6 — 8.6 — 9.0 — 8.6 ns

— 6.8 — 5.9 — 6.0 — 6.4 — 6.0 ns

— 10.2 — 8.5 — 8.6 — 9.1 — 7.9 ns

T Outputs (TJ = 85 °C, VDD = min, CL = 50 pF)

T PFU CK to Pad Delay (DOUT[3:0] to

PAD):

C Fast

DOUT_DEL(F) — 6.2 — 5.5 — 5.0 — 4.4 — 3.3 ns

N Slewlim

DOUT_DEL(SL) — 8.4 — 7.4 — 6.4 — 5.6 — 4.1 ns

Sinklim

DOUT_DEL(SI) — 10.5 — 9.4 — 9.5 — 8.3 — 7.2 ns

Output to Pad Delay (OUT[3:0] to

E PAD):

O Fast

Slewlim

L Sinklim

OUT_DEL(F) — 4.0 — 3.6 — 3.1 — 2.7 — 2.3 ns

OUT_DEL(SL) — 6.3 — 5.5 — 4.5 — 3.9 — 3.1 ns

OUT_DEL(SI) — 7.2 — 7.5 — 7.6 — 6.5 — 6.2 ns

3-state Enable Delay (TS[3:0] to

E C PAD):

Fast

Slewlim

Sinklim

TS_DEL(F)

TS_DEL(SL)

TS_DEL(SI)

— 4.7 — 4.0 — 3.5 — 3.1 — 2.5 ns

— 7.0 — 6.3 — 5.2 — 4.7 — 3.7 ns

— 7.9 — 8.4 — 9.3 — 8.0 — 7.6 ns

S IS Notes:

If the input buffer is placed in delay mode, the chip hold time to the nearest PFU latch is guaranteed to be 0 if the clock is routed using the

primary clock network; (TJ = all, VDD = all). It should also be noted that any signals routed on the clock lines or using the TRIDI buffers directly

D from the input buffer do not get delayed at any time.

The delays for all input buffers assume an input rise/fall time of ≤1 V/ns.

158

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