AD5280BRU200 查看數據表（PDF） - Analog Devices
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AD5280BRU200 Datasheet PDF : 20 Pages
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AD5280/AD5282
Parameter
Symbol Conditions
Min Typ1 Max Unit
INTERFACE TIMING CHARACTERISTICS Applies to all parts6, 10
SCL Clock Frequency
fSCL
tBUF Bus Free Time between STOP and START t1
tHD:STA Hold Time (Repeated START)
t2
1.3
After this period, the first 0.6
clock pulse is generated
tLOW Low Period of SCL Clock
t3
1.3
tHIGH High Period of SCL Clock
t4
0.6
tSU:STA Setup Time for START Condition
t5
0.6
tHD:DAT Data Hold Time
t6
tSU:DAT Data Setup Time
t7
100
tF Fall Time of Both SDA and SCL Signals
t8
tR Rise Time of Both SDA and SCL Signals
t9
tSU:STO Setup Time for STOP Condition
t10
0.6
400
kHz
µs
µs
µs
50
µs
µs
0.9
µs
ns
300
ns
300
ns
µs
NOTES
1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = –5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = No connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD ϫ VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = 5 V.
10See timing diagram for location of measured values.
Specifications subject to change without notice.
REV. 0
–3–
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