AD9572ACPZPEC-RL(Rev0) 查看數據表（PDF） - Analog Devices

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AD9572ACPZPEC-RL
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

AD9572

LVPECL CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 3.

Jitter Integration

Bandwidth (Typ)

12 kHz to 20 MHz

1.875 MHz to

20 MHz

637 kHz to 10 MHz

200 kHz to 10 MHz

12 kHz to 35 MHz

100 MHz

33M = Off/On

608/564

337/378

106.25 MHz

33M = Off/On

418/451

227/232

125 MHz

33M = Off/On

444/2200

242/2200

523 (off only)

156.25 MHz

33M = Off/On

420/461

200/277

Unit

fS rms

fS rms

fS rms

fS rms

fS rms

Test Conditions/Comments

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVPECL output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVPECL output frequency combinations

are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×

106.25 MHz

CMOS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 4.

Jitter Integration Bandwidth

12 kHz to 5 MHz

200 kHz to 5 MHz

25 MHz

781

764

33.3 MHz

417

524

Unit

fS rms

fS rms

Test Conditions/Comments

REFERENCE INPUT

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given

over full VS and TA (−40°C to +85°C) variation.

Table 5.

Parameter

CLOCK INPUT (REFCLK)

Input Frequency

Input High Voltage

Input Low Voltage

Input Current

Input Capacitance

Min

Typ

25

2.0

−1.0

2

Max

Unit

Test Conditions/Comments

MHz

V

0.8

V

+1.0

μA

pF

Rev. 0 | Page 5 of 20

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