AD9572ACPZPEC-RL(Rev0) 查看數據表（PDF） - Analog Devices

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AD9572ACPZPEC-RL
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

AD9572

TIMING DIAGRAMS

DIFFERENTIAL

80%

20%

LVPECL

tRP

tFP

Figure 3. LVPECL Timing, Differential

DIFFERENTIAL

80%

20%

LVDS

tRL

tFL

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

20%

CMOS

5pF LOAD

tRC

tFC

Figure 5. CMOS Timing, Single-Ended, 5 pF Load

Rev. 0 | Page 8 of 20

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