ADE3800XT 查看數據表（PDF） - STMicroelectronics

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ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

The 4 delay counters measure the time (in XCLKs) between the leading and trail edges of the SOG

signals, as follows:

d1: delay count from SOG[2] falling edge to SOG[1] falling edge

d2: delay count from SOG[1] falling edge to SOG[0] falling edge

d3: delay count from SOG[0] rising edge to SOG[1] rising edge

d4: delay count from SOG[1] rising edge to SOG[2] rising edge

If there is no leading edge for a particular delay counter, the result is 0.

If both edges are within the same XCLK period, the result is 1.

When the counter reaches a value of 0F, it stops.

The delay and activity registers are used together to tune the SOG sampling level.

The delay measurements are controlled by the activity detection control registers which may be

used to select either:

● One-shot: one sync pulse measurement; when done, hold result until next measurement is

started; or

● Free-run: continuously measures, results are dynamically updated.

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