ADE3800XT 查看數據表（PDF） - STMicroelectronics

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ADE3800XT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

4.4 Analog Dithering (ADTH)

Note:

The ADTH block generates a 3-bit dither pattern ADTH_OUT[2:0] to tune the 10-bit resolution of the

ADC block.

ADTH_OUT[2:0] is not a register but the generated 3-bit dither output of the ADTH block.

4.4.1

Function

The ADTH block consists of a 32x32x3 bit look up table (LUT). It represents one dither matrix, which

can be read using a programmable addressing technique as well as a programmable output

amplitude control. When ADTH_MAT_CTRL[0] is zero or during the clamp pulse ADTH_OUT[2:0] =

3. During vertical blanking ADTH_OUT[2:0] is set to ADTH_TEST_DITHER[2:0] to provide a

feedback mechanism for calibration.

4.4.2

Note:

Addressing Technique

The ADTH block offers a programmable addressing technique to generate various temporal dither

patterns. ADTH_FRAME_CTRL [7:4] is a 4-bit increment value, which defines the horizontal/vertical

displacement of the dither matrix from frame to frame (precisely at rising edge of CLAMP_IN and at

falling edge of VENAB).

After (ADTH_FRAME_CTRL [3:0] + 1) number of frames the horizontal/vertical displacement position

will be reset to zero/zero, only when ADTH_FRAME_CTRL [3:0]> 0.

To set the frame accumulator to zero, program ADTH_FRAME_CTRL [7:4] to zero and program

ADTH_FRAME_CTRL [3:0] to 1. ADTH_FRAME_CTRL [7:4] can be independently activated in the

horizontal and vertical dimensions using ADTH_MAT_CTRL [2] and ADTH_MAT_CTRL [3],

respectively.

4.4.3

Output Amplitude Control

The 3-bit LUT output value can be scaled to a reduced dither amplitude using ADTH_MAT_CTRL

[5:4]. After adding the ADTH_MAT_CTRL [7:6] to the (reduced) dither amplitude the final 3-bit

amplitude is output as ADTH_OUT[2:0].

4.4.4

Miscellaneous

During the ADC clamp pulse, the output of the ADTH block is muted; that is the output value is set

to 3 (ADTH_OUT[2:0] = 3). In addition, ADTH_CLAMP_CTRL[7:4] delays the clamp pulse by 0 to

15 clock cycles while muting, and ADTH_CLAMP_CTRL[3:0] adds 0 to 15 clock cycles of muting

after the falling edge of the clamp pulse.

For AFE dither calibration, ADTH_OUT[2:0] can be programmed via ADTH_TEST_DITHER to a

static value during vertical blanking.

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