ADE3800SXT 查看數據表（PDF） - STMicroelectronics

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ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

Register Name

SCL_H_KERNEL_0

SCL_H_KERNEL_1

SCL_H_KERNEL_2

SCL_H_KERNEL_3

SCL_H_KERNEL_4

SCL_H_KERNEL_5

SCL_H_KERNEL_6

SCL_H_KERNEL_7

SCL_H_KERNEL_8

SCL_H_KERNEL_NORM

SCL_V_KERNEL_0

SCL_V_KERNEL_1

SCL_V_KERNEL_2

SCL_V_KERNEL_3

SCL_V_KERNEL_4

SCL_V_KERNEL_NORM

SCL_BGCOLOR_B

SCL_BGCOLOR_G

SCL_BGCOLOR_R

SCL_BGCOLOR_CTRL

SCL_PTR_PRE_L

SCL_PTR_PRE_U

Table 23: Scale Registers (Sheet 2 of 3)

Addr R/W Bits Rst

Description

0A10

0A11

0A12

0A13

0A14

0A15

0A16

0A17

0A18

0A19

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 40

0A1A R/W [7:0] 00

0A1B R/W [7:0] 00

0A1C R/W [7:0] 00

0A1D R/W [7:0] 00

0A1E R/W [7:0] 00

0A1F R/W [7:0] 40

0A20

0A21

0A22

0A23

R/W [7:0] 00

R/W [7:0] 00

R/W [7:0] 00

R/W [7]

00

R/W [4]

R/W [3:2]

R/W [1:0]

0A24 R

[7:0] 00

0A25 R

[3:0] 00

Horizontal filter kernel

2’s complement, signed numbers ranging from –2 to +1

63/64

2’s complement, signed number used to normalize the H

filter kernel (usually 64)

Vertical filter kernel

2’s complement, signed numbers ranging from –2 to +1

63/64

Has a ½ line shift compared to hkernel and must be

programmed to a 2 line kernel when in_hpixel > 1024.

2’s complement, signed number used to normalize the V

filter kernels (usually 64)

Blue component of background color, refer to Figure 21

Green component of background color, refer to Figure 21

Red component of background color, refer to Figure 21

1: force background color

Mute color select:

0*: black

1: use background color

when SMEAS_STATUS_RANGE[7] is high

0*: line replicate 1

1: line replicate 2

2: line replicate 3

3: vertical border blend

0*: pixel replicate 1

1: pixel replicate 2

2: pixel replicate 3

3: horizontal border blend

The minimum difference of the write pointer and the first

of three read pointers; updated every frame

LSB = 4 pixels

Not valid when SCL_CONTROL[3] = 1

55/138

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