ADE3800SXT 查看數據表（PDF） - STMicroelectronics
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ADE3800SXT
STMicroelectronics
ADE3800SXT Datasheet PDF : 138 Pages
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Register Description by Block
ADE3800
Register Name
SCL_PTR_POST_L
SCL_PTR_POST_U
SCL_CONTROL
SCL_VCOUNT
SCL_HTOTAL_L
SCL_HTOTAL_U
SCL_VTOTAL_MIN_L
SCL_VTOTAL_MIN_U
SCL_VTOTAL_MAX_L
SCL_VTOTAL_MAX_U
SCL_TRIGGER_DLY_L
SCL_TRIGGER_DLY_M
SCL_TRIGGER_DLY_U
SCL_LINE_START_L
SCL_LINE_START_U
SCL_CONTEXT_0
SCL_CONTEXT_1
Table 23: Scale Registers (Sheet 3 of 3)
Addr R/W Bits Rst
Description
0A26 R
[7:0] 00
0A27
0A28
R
[3:0] 00
R/W [4]
00
R/W [3]
R/W [2]
R/W [1]
R/W [0]
0A29 R
[7:0]
0A2A R/W [7:0] 00
0A2B R/W [3:0] 00
0A2C R/W [7:0] 00
0A2D R/W [3:0] 00
0A2E R/W [7:0] 00
0A2F R/W [3:0] 00
0A30
0A31
0A32
R/W [7:0] 00
R/W [7:0] 00
R/W [3:0] 00
0A33 R/W [7:0]
0A34
0A35
0A36
R/W [3:0]
R/W [6:1] 00
R/W [0]
R/W [7:6] 00
R/W [5:4]
R/W [3:0]
The minimum difference of the write pointer and the last
of three read pointers; updated every frame
LSB = 4 pixels
allow trigger delay count to be retriggered by SMUX vtrig
(normal = 0)
use two tap vertical filter
0*: in hpixel <= 1024
1: in_hpixel > 1024
ptr_pre is invalid in this case
allow output sequencer to be retriggered before
vtotal_min (normal = 0)
completes the current frame then stops the sequencer.
Poll the vcount register to determine when frame has
stopped.
enable scaler timing engine (output sequencer)
output sequencer vertical counter >> 4
desired output htotal - 1
out_htotal should be even
note: out_henab should be a multiple of 4 for RSDS dual
minimum vcount before a new frame can be started
vcount at which the output sequencer will self trigger to
maintain a minimum frame rate to the panel
time in xclks from SMUX vtrig to when vcount/hcount of
the output sequencer are reset to 0,0.
pipe start value
= 4.5 -origin_hpos*4096/scale_factor_h -(21.5+5*4096/
pipe_rate)*sclk_period/dotclk_period
If pipe_rate = 0, use 4096.
context sharp offset
enable context function (normal)
context smooth slope (recommended = 1, 2, 3)
context sharp slope
context sharp clip
For proper scale operation, the SCLK frequency must be programmed so that:
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