AT89C51RC2-3CSCM(2003) 查看數據表（PDF） - Atmel Corporation
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AT89C51RC2-3CSCM Datasheet PDF : 125 Pages
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Oscillator
Registers
To optimize the power consumption and execution time needed for a specific task, an
internal, prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Table 13. CKRL Register
CKRL – Clock Reload Register (97h)
7
CKRL7
6
CKRL6
5
CKRL5
4
CKRL4
3
CKRL3
2
CKRL2
1
CKRL1
0
CKRL0
Bit Number
7:0
Mnemonic
CKRL
Reset Value = 1111 1111b
Not bit addressable
Description
Clock Reload Register
Prescaler value
Table 14. PCON Register
PCON – Power Control Register (87h)
7
6
5
SMOD1 SMOD0
-
4
3
2
1
0
POF
GF1
GF0
PD
IDL
Bit Number
7
6
5
4
3
2
1
0
Bit Mnemonic Description
SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
POF
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
General-purpose Flag
GF1
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
General-purpose Flag
GF0
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
Power-down Mode bit
PD
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode bit
IDL
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b Not bit addressable
12 AT89C51RB2/RC2
4180B–8051–04/03
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