AT89C51RB2/RC2
Table 48. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
6
5
4
-
-
-
-
3
2
1
-
SPIL
-
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPIL
SPI Interrupt Priority Bit
see SPIH for priority level.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
KBDL
Keyboard Interrupt Priority Bit
see KBDH for priority level.
Reset Value = XXXX X000b
Bit addressable
0
KBDL
61
4180E–8051–10/06