AT89C51RC2-3CSCM 查看數據表（PDF） - Atmel Corporation

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AT89C51RC2-3CSCM

8-bit Microcontroller with 16K/32K Bytes Flash

Atmel Corporation 

Functional Description

Figure 26 shows a detailed structure of the SPI Module.

Figure 26. SPI Module Block Diagram

Internal Bus

FCLK PERIPH

SPDAT

Shift Register

7 65 4 3210

Clock

/4

/8

Divider

/16

/32

/64

/128

Clock

Select

Receive Data Register

Clock

Logic

Pin

Control

Logic

M

S

MOSI

MISO

SCK

SS

Operating Modes

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

SPI Interrupt Request

SPI

Control

8-bit bus

1-bit signal

SPSTA

SPIF WCOL - MODF -

-

-

-

The Serial Peripheral Interface can be configured in one of the two modes: Master

mode or Slave mode. The configuration and initialization of the SPI Module is made

through one register:

• The Serial Peripheral Control register (SPCON)

Once the SPI is configured, the data exchange is made using:

• SPCON

• The Serial Peripheral STAtus register (SPSTA)

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave

device responds by sending data to the Master device via the MISO line. This implies

full-duplex transmission with both data out and data in synchronized with the same clock

(Figure 27).

70 AT89C51RB2/RC2

4180E–8051–10/06

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