C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

12.2. Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are

two separate memory spaces: program memory and data memory. Program and data memory share the

same address space but are accessed via different instruction types. There are 256 bytes of internal data

memory and 64k bytes of internal program memory address space implemented within the CIP-51. The

CIP-51 memory organization is shown in Figure 12.2.

PROGRAM/DATA MEMORY

(FLASH)

0x1007F

0x10000

C8051F040/1/2/3/4/5

Scrachpad Memory

(DATA only)

0xFE00

0xFDFF

RESERVED

0xFF

0x80

0x7F

64 kB

Flash

(In-System

Programmable in 512

Byte Sectors)

0x30

0x2F

0x20

0x1F

0x00

DATA MEMORY (RAM)

INTERNAL DATA ADDRESS SPACE

Upper 128 RAM

(Indirect Addressing

Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

Special Function

Registers

(Direct Addressing Only)

0

1

2

3

F

Lower 128 RAM

(Direct and Indirect

Addressing)

Up To

256 SFR Pages

0x0000

0x1007F

0x10000

C8051F046/7

Scrachpad Memory

(DATA only)

0x8000

0x7FFF

RESERVED

32 kB

Flash

(In-System

Programmable in 512

Byte Sectors)

0x0000

0xFFFF

EXTERNAL DATA ADDRESS SPACE

Off-chip XRAM space

0x1000

0x0FFF

0x0000

XRAM - 4096 Bytes

(accessable using MOVX

instruction)

Figure 12.2. Memory Map

12.2.1. Program Memory

The CIP-51 has a 64 kB program memory space. The MCU implements 64 kB (C8051F040/1/2/3/4/5) and

32 kB (C8051F046/7) of this program memory space as in-system re-programmed Flash memory, orga-

nized in a contiguous block from addresses 0x0000 to 0xFFFF (C8051F040/1/2/3/4/5) and 0x0000 to

0x7FFF (C8051F046/7). Note: 512 bytes from 0xFE00 to 0xFFFF (C8051F040/1/2/3/4/5 only) of this mem-

ory are reserved for factory use and are not available for user program storage.

Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory

by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-

vides a mechanism for the CIP-51 to update program code and use the program memory space for non-

volatile data storage. Refer to Section “15. Flash Memory” on page 179 for further details.

Rev. 1.5

133

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