C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

0x0F

(Port 5)

C8051F040/1/2/3/4/5/6/7

SFR Page

Stack SFR's

SFRPAGE

SFRNEXT

SFRLAST

Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5

While CIP-51 executes in-line code (writing values to Port 5 in this example), an ADC2 Window Compara-

tor Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current

SFR Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to

access ADC2’s SFR’s is then automatically placed in the SFRPAGE register (SFR Page 0x02). SFRPAGE

is considered the “top” of the SFR Page Stack. Software can now access the ADC2 SFR’s. Software may

switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR

to access SFR’s that are not on SFR Page 0x02. See Figure 12.5.

Rev. 1.5

137

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