C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR.

When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if

SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less

than 50 µs (see SFR Definition 19.2, SMBus0 Clock Rate Register).

When the TOE bit in SMB0CN is set to logic 1, Timer 4 is used to detect SCL low timeouts. If Timer 4 is

enabled (see Section “23.2. Timer 2, Timer 3, and Timer 4” on page 295), Timer 4 is forced to reload

when SCL is high, and forced to count when SCL is low. With Timer 4 enabled and configured to overflow

after 25 ms (and TOE set), a Timer 4 overflow indicates a SCL low timeout; the Timer 4 interrupt service

routine can then be used to reset SMBus0 communication in the event of an SCL low timeout.

246

Rev. 1.5

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