C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Master

Device 1

NSS

MISO

MOSI

SCK

GPIO

GPIO

MISO

MOSI

SCK

NSS

Master

Device 2

Figure 20.2. Multiple-Master Mode Connection Diagram

Master

Device MISO

MOSI

SCK

Slave

MISO Device

MOSI

SCK

Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram

Master

Device

GPIO

MISO

MOSI

SCK

NSS

MISO

MOSI

SCK

NSS

Slave

Device

MISO

MOSI

SCK

NSS

Slave

Device

Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram

258

Rev. 1.5

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