C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate

R/W

SCR7

Bit7

R/W

SCR6

Bit6

R/W

SCR5

Bit5

R/W

SCR4

Bit4

R/W

SCR3

Bit3

R/W

SCR2

Bit2

R/W

SCR1

Bit1

R/W

Reset Value

SCR0 00000000

Bit0

SFR Address: 0x9D

SFR Page: 0

Bits 7-0: SCR7-SCR0: SPI0 Clock Rate

These bits determine the frequency of the SCK output when the SPI0 module is configured

for master mode operation. The SCK clock frequency is a divided version of the system

clock, and is given in the following equation, where SYSCLK is the system clock frequency

and SPI0CKR is the 8-bit value held in the SPI0CKR register.

fSCK = 2------------S--S--P-Y---I-S-0--C-C----L-K--K--R-----+-----1----

for 0 <= SPI0CKR <= 255

Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,

fSCK

=

---2---0---0---0---0---0---0----

2  4 + 1

fSCK = 200kHz

Rev. 1.5

263

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