C8051F045 查看數據表（PDF） - Silicon Laboratories
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C8051F045 Datasheet PDF : 328 Pages
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C8051F040/1/2/3/4/5/6/7
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 204 for information on selecting
and configuring external I/O pins). Clearing C/T0 selects the clock defined by the T0M bit (CKCON.3).
When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the
source selected by the Clock Scale bits in CKCON (see SFR Definition 23.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /
INT0 (see Section “12.3.5. Interrupt Register Descriptions” on page 156), facilitating pulse width mea-
surements.
TR0
GATE0
0
X
1
0
1
1
1
1
Note: X = Don't Care
/INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1.
Pre-scaled Clock
SYSCLK
T0
Crossbar
GATE0
CKCON
TT SS
1 0 CC
MM A A
10
TMOD
GCT TGCT T
A / 11A / 00
T T MMT TMM
E110E010
1
0
0
0
1
1
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
/INT0
Figure 23.1. T0 Mode 0 Block Diagram
23.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
288
Rev. 1.5
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