C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

23.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload

Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start

value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF

to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer

0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not

changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be cor-

rect. When in Mode 2, Timer 1 operates identically to Timer 0.

Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the

TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0

is low.

CKCON

TT SS

1 0 CC

MM A A

10

TMOD

GCT TGCT T

A / 11A / 00

T T MM T T MM

E110E010

1

0

Pre-scaled Clock

0

0

SYSCLK

1

1

T0

Crossbar

TR0

GATE0

/INT0

TCLK

TL0

(8 bits)

TH0

(8 bits)

Reload

Figure 23.2. T0 Mode 2 Block Diagram

TF1

TR1

TF0

Interrupt

TR0

IE1

IT1

IE0

IT0

Rev. 1.5

289

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