C8051F045 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

23.2.2. Capture Mode

In Capture Mode, Timer n will operate as a 16-bit counter/timer with capture facility. When the Timer Exter-

nal Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX input pin

causes the 16-bit value in the associated timer (TMRnH, TMRnL) to be loaded into the capture registers

(RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6)

will be set to ‘1’ and an interrupt will occur if the interrupt is enabled. See Section “12.3. Interrupt Han-

dler” on page 153 for further information concerning the configuration of interrupt sources.

As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow

Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config-

ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to

decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to

0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will

occur if enabled.

Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn

(TMRnCN.0) and the Timer n Run Control bit TRn (TMRnCN.2) to logic 1. The Timer n respective External

Enable EXENn (TMRnCN.3) must also be set to logic 1 to enable captures. If EXENn is cleared, transi-

tions on TnEX will be ignored.

2

SYSCLK

12

External Clock

(XTAL1)

Tn

8

0

1

Crossbar

TRn

EXENn

TnE

Crossbar

X

TMRnCF

TTTTD

n nOnC

MMGO E

1 0 nEN

0xFF

0xFF

Toggle Logic

0

1

Tn

(Port Pin)

TCLK TMRnL TMRnH

RCAPnL RCAPnH

CP/RLn

C/Tn

TRn

EXENn

EXFn

TFn

Interrupt

Figure 23.4. Tn Capture Mode Block Diagram

296

Rev. 1.5

Share Link: