C8051F045 查看數據表（PDF） - Silicon Laboratories
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C8051F045 Datasheet PDF : 328 Pages
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C8051F040/1/2/3/4/5/6/7
5. 12-Bit ADC (ADC0, C8051F040/1 Only)
The ADC0 subsystem for the C8051F040/1 consists of a 9-channel, configurable analog multiplexer
(AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in
Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under
software control via the Special Function Registers shown in Figure 5.1. The voltage reference used by
ADC0 is selected as described in Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 for
C8051F040 devices, or Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117 for
C8051F041 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power
shutdown when this bit is logic 0.
ADC0GTH
HV
Input
Port 3
I/O Pins
Analog
Input
Pins
9-to-1
AMUX
(SE or
DIFF)
ADC0GTL
ADC0LTH
ADC0LTL
24
AD0EN
AV+
X
+
-
AGND
AV+
12-Bit
SAR
12
ADC
Comb.
Logic
12
AD0WINT
TEMP
SENSOR
AGND
00
Start Conversion 01
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AMX0CF
AMX0SL
ADC0CF
ADC0CN
Figure 5.1. 12-Bit ADC0 Functional Block Diagram
5.1. Analog Multiplexer and PGA
The analog multiplexer can input analog signals to the ADC from four external analog input pins (AIN0.0 -
AIN0.3), Port 3 port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, or
an internally connected on-chip temperature sensor (temperature transfer function is shown in Figure 5.6).
AMUX input pairs can be programmed to operate in either differential or single-ended mode. This allows
the user to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 5.2), the Configuration
register AMX0CF (SFR Definition 5.1), and the Port Pin Selection register AMX0PRT (SFR Definition 5.3).
Table 5.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-
ration register, ADC0CF (SFR Definition 5.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
Rev. 1.5
47
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