C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits)

0000

0000 AIN0.0

0001

+(AIN0.0)

-(AIN0.1)

0010 AIN0.0

0011

+(AIN0.0)

-(AIN0.1)

0100 AIN0.0

0101

+(AIN0.0)

-(AIN0.1)

0110 AIN0.0

0111

+(AIN0.0)

-(AIN0.1)

1000 AIN0.0

1001

+(AIN0.0)

-(AIN0.1)

1010 AIN0.0

1011

+(AIN0.0)

-(AIN0.1)

1100 AIN0.0

1101

+(AIN0.0)

-(AIN0.1)

1110 AIN0.0

1111

+(AIN0.0)

-(AIN0.1)

0001

AIN0.1

AIN0.1

AIN0.1

AIN0.1

AIN0.1

AIN0.1

AIN0.1

AIN0.1

0010

AIN0.2

AIN0.2

+(AIN0.2)

-(AIN0.3)

+(AIN0.2)

-(AIN0.3)

AIN0.2

AIN0.2

+(AIN0.2)

-(AIN0.3)

+(AIN0.2)

-(AIN0.3)

AIN0.2

AIN0.2

+(AIN0.2)

-(AIN0.3)

+(AIN0.2)

-(AIN0.3)

AIN0.2

AIN0.2

+(AIN0.2)

-(AIN0.3)

+(AIN0.2)

-(AIN0.3)

AMX0AD3-0

0011 0100 0101

AIN0.3

HVDA

AGND

AIN0.3

HVDA

AGND

HVDA

AGND

AIN0.3

AIN0.3

AIN0.3

HVDA

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

HVDA

AGND

AGND

AIN0.3

HVDA

AGND

HVDA

AGND

AIN0.3

AIN0.3

HVDA

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

+(HVDA)

-(HVREF)

AGND

0110

P3EVEN

0111

P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

P3EVEN P3ODD

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD)

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD

+P3EVEN

-P3ODD

1xxx

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

TEMP

SENSOR

Note: “P3EVEN” denotes even numbered and “P3ODD” odd numbered Port 3 pins selected in the AMX0PRT

register.

50

Rev. 1.5

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