C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

A. ADC Timing for External Trigger Source

CNVSTR

(AD0CM[1:0]=10)

SAR

Clocks

1

2

3

4

5

6

7

8

9

1

0

1

1

1

2

1

3

1

4

1

5

1

6

ADC0TM=1

Low Power

or Convert

Track

Convert

ADC0TM=0

Track Or Convert

Convert

Low Power Mode

Track

B. ADC Timing for Internal Trigger Sources

Timer 2, Timer 3 Overflow;

Write '1' to AD0BUSY

(AD0CM[1:0]=00, 01, 11)

SAR

Clocks

1

2

3

4

5

6

7

8

9

1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

ADC0TM=1

Low Power

or Convert

Track

Convert

SAR

Clocks

1

2

3

4

5

6

7

8

9

1

0

1

1

1

2

1

3

1

4

1

5

1

6

ADC0TM=0

Track or

Convert

Convert

Low Power Mode

Track

Figure 5.4. 12-Bit ADC Track and Conversion Example Timing

Rev. 1.5

55

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