C8051F045 查看數據表（PDF） - Silicon Laboratories

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产品描述 (功能)

生产厂家

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

A. ADC Timing for External Trigger Source

CNVSTR2/CNVSTR0

(AD2CM[2:0]=010)

SAR2 Clocks

123456789

AD2TM=1

Low Power

or Convert

Track

Convert

Low Power Mode

AD2TM=0

Track or Convert

Convert

Track

B. ADC Timing for Internal Trigger Source

Write '1' to AD2BUSY,

Timer 3 Overflow,

Timer 2 Overflow,

Write '1' to AD0BUSY

(AD2CM[2:0]=000, 001, 011, 0xx)

1 2 3 4 5 6 7 8 9 10 11 12

SAR2 Clocks

Low Power

AD2TM=1 or Convert

Track

Convert

Low Power Mode

SAR2 Clocks

123456789

AD2TM=0

Track or

Convert

Convert

Track

Figure 7.2. ADC2 Track and Conversion Example Timing

Rev. 1.5

93

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