C8051F045 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

7.2.3. Settling Time Requirements

A minimum tracking time is required before an accurate conversion can be performed. This tracking time is

determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis-

tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit.

The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1.

Note: An absolute minimum settling time of 0.8 µs required after any MUX selection. Note that in low-

power tracking mode, three SAR2 clocks are used for tracking at the start of every conversion. For most

applications, these three SAR2 clocks will meet the tracking requirements.

t

=

ln





S-2---An--



RTOTALCSAMPLE

Equation 7.1. ADC2 Settling Time Requirements

Where:

SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)

t is the required settling time in seconds

RTOTAL is the sum of the ADC2 MUX resistance and any external source resistance.

n is the ADC resolution in bits (8).

MUX Select

AIN2.x

RMUX = 5k

CSAMPLE = 10pF

RCInput= RMUX * CSAMPLE

Figure 7.3. ADC2 Equivalent Input Circuit

94

Rev. 1.5

Share Link: