C8051F38B-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

SFR Definition 16.4. EIP1: Extended Interrupt Priority 1

Bit

7

6

5

4

3

2

1

Name PT3

PCP1

PCP0 PPCA0 PADC0 PWADC0 PUSB0

Type R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

SFR Address = 0xF6; SFR Page = All Pages

Bit Name

Function

7

PT3 Timer 3 Interrupt Priority Control.

This bit sets the priority of the Timer 3 interrupt.

0: Timer 3 interrupts set to low priority level.

1: Timer 3 interrupts set to high priority level.

6 PCP1 Comparator1 (CP1) Interrupt Priority Control.

This bit sets the priority of the CP1 interrupt.

0: CP1 interrupt set to low priority level.

1: CP1 interrupt set to high priority level.

5 PCP0 Comparator0 (CP0) Interrupt Priority Control.

This bit sets the priority of the CP0 interrupt.

0: CP0 interrupt set to low priority level.

1: CP0 interrupt set to high priority level.

4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.

This bit sets the priority of the PCA0 interrupt.

0: PCA0 interrupt set to low priority level.

1: PCA0 interrupt set to high priority level.

3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.

This bit sets the priority of the ADC0 Conversion Complete interrupt.

0: ADC0 Conversion Complete interrupt set to low priority level.

1: ADC0 Conversion Complete interrupt set to high priority level.

2 PWADC0 ADC0 Window Comparator Interrupt Priority Control.

This bit sets the priority of the ADC0 Window interrupt.

0: ADC0 Window interrupt set to low priority level.

1: ADC0 Window interrupt set to high priority level.

1 PUSB0 USB (USB0) Interrupt Priority Control.

This bit sets the priority of the USB0 interrupt.

0: USB0 interrupt set to low priority level.

1: USB0 interrupt set to high priority level.

0 PSMB0 SMBus0 Interrupt Priority Control.

This bit sets the priority of the SMB0 interrupt.

0: SMB0 interrupt set to low priority level.

1: SMB0 interrupt set to high priority level.

0

PSMB0

R/W

0

124

Rev. 1.4

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