CS4952 查看數據表（PDF） - Cirrus Logic
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CS4952 Datasheet PDF : 44 Pages
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CS4952/53
PROGRAMMING
Host Control Interface
The CS4952/3 host control interface can be config-
ured for I2C or 8-bit parallel operation. The
CS4952/3 will default to I2C operation when the
RD and WR pins are both tied low at power up. The
RD and WR pins are active for 8-bit parallel oper-
ation only.
I2C Interface
The CS4952/3 provides an I2C interface for access-
ing the internal control and status registers. External
pins are a bidirectional data pin (SDA) and a serial
input clock (SCL). The protocol follows the I2C
specifications. A complete data transfer is shown in
Figure 14. Note that this I2C interface will work in
Slave Mode only - it is not a bus master.
SDA and SCL are connected via an external
pull-up resistor to a positive supply voltage. When
the bus is free, both lines are high. The output stag-
es of devices connected to the bus must have an
open-drain or open-collector in order to perform
the wired-AND function. Data on the I2C bus can
be transferred at a rate of up to 400 kbits/sec in fast
mode. The number of interfaces to the bus is solely
dependent on the limiting bus capacitance of
400 pF. When 8-bit parallel interface operation is
being used, SDA and SCL can be tied directly to
ground.
The I2C bus address for the CS4952/3 is program-
mable via register I2C_ADR (0x0F).
8-bit Parallel Interface
The CS4952/3 is equipped with a full 8-bit parallel
microprocessor write and read control port. Along
with the PDAT [7:0] pins the control port interface
is comprised of host read RD and host write WR
active low strobes and host address enable ADDR
which, when low, enables unique address register
accesses. The control port is used to access internal
registers which configure the CS4952/3 for various
modes of operation. The internal registers are
uniquely addressed via an address register. The ad-
dress register is accessed during a host write cycle
with the WR and ADDR pins set low. Host write
cycles with ADDR set high will write the 8-bits on
the PDAT [7:0] pins into the register currently se-
lected by the address register. Likewise read cycles
occur with RD set low and ADDR set high will re-
turn the register contents selected by the address
register. Reference the detailed electrical timing
parameter section of this data sheet for exact host
parallel interface timing characteristics and specifi-
cations. When I2C interface operation is being
used, RD and WR must be tied to ground.
PDAT [7:0] are available to be used for GPIO op-
eration in I2C host interface mode.
I 2 C Protocol
SDA
SCL
A
1-7
89
Start Address R/W ACK
1-7
89
Data
ACK
1-7
8
Data
Note: I 2 C transfers data always with MSB first, LSB last
Figure 14. I2C Data Transfer
9
ACK
P
Stop
DS223PP2
27
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