CS4952 查看數據表（PDF） - Cirrus Logic

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产品描述 (功能)

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CS4952

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4952/53

Register Description

A set of internal registers are available for control-

ling the operation of the CS4952/3. The registers

extend from internal address 0x00 through 0x3D.

Table 5 shows a complete list of these registers and

their internal addresses. Note that this table and the

subsequent register description section describe the

full register map for CS4952 only. A complete

CS4953 register set description is only available to

Macrovision ACP-PPV Licensed Buyers.

Address

0x00

0x01

0x02

0x03

0x04

0x05 - 0x06

0x07

0x08

0x09

0x0A

0x0B - 0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D - 0x3A

0x3B

0x3C

0x3D

Register Name

CONTROL_0

CONTROL_1

CONTROL_2

RESERVED

DAC

RESERVED

STATUS

BKG_COLOR

GPIO_CTRL_REG

GPIO_DATA_REG

RESERVED

C_AMP

Y_AMP

I2C_ADR

SC_AMP

SC_SYNTH0

SC_SYNTH1

SC_SYNTH2

SC_SYNTH3

HUE_LSB

HUE_MSB

RESERVED

CC_EN

CC_21_1

CC_21_2

CC_284_1

CC_284_2

RESERVED

INT_EN

INT_CLR

ID_REG

Type

r/w

r/w

r/w

r/w

read only

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

read only

Table 5. Control Register Map

Default Value

01h

04h

00h

F0h

00h

03h

00h

80h

80h

n/a

1Ch

3Eh

F8h

E0h

43h

00h

00h

00h

00h

00h

00h

00h

00h

00h

n/a

28

DS223PP2

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