CS4955-CQZ 查看數據表（PDF） - Cirrus Logic

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CS4955-CQZ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

RD

PADR

Trd

Trpw

Trah

PDAT[7:0]

Tas

Trda

Trdh

Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle

Twpw

Twr

WR

PADR

Twac

PDAT[7:0]

Tas

Twds Twdh

Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle

8.2 Register Description

A set of internal registers are available for control-

ling the operation of the CS4954/5. The registers

extend from internal address 0×00 through 0×5A.

Table 9 shows a complete list of these registers and

their internal addresses. Note that this table and the

subsequent register description section describe the

full register map for the CS4954 only. A complete

CS4955 register set description is available only to

MacrovisionTM ACP-PPV Licensed Buyers.

8.2.1 Control Registers

Address

0×00

0×01

0×02

0×03

0×04

0×05

0×06

0×07

0×08

Register Name

control_0

control_1

control_2

control_3

control_4

control_5

control_6

RESERVED

bkg_color

Table 9. Control Registers

Type

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

Default value

01h

02h

00h

00h

3Fh

00h

00h

03h

36

DS278F6

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