DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CS4955-CQZ 查看數據表(PDF) - Cirrus Logic

零件编号
产品描述 (功能)
生产厂家
CS4955-CQZ
Cirrus-Logic
Cirrus Logic 
CS4955-CQZ Datasheet PDF : 60 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
CS4954 CS4955
Address
0×34
0×35 - 0×59
0×5A
0×61 - 0×7F
Control Register 0
Address
Bit Number
Bit Name
Default
0×00
7
0
Register Name
STATUS_0
RESERVED
STATUS_1
RESERVED
Type
read only
read only
Table 9. Control Registers (Continued)
CONTROL_0 Read/Write
6
5
TV_FMT
0
0
4
MSTR
0
Default Value = 01h
3
CCIR656
0
2
PROG
0
Default value
04h
1
IN_MODE
0
0
CBCR_UV
1
Bit
Mnemonic
Function
selects the TV display format
000:
NTSC-M CCIR601 timing (default)
001:
NTSC-M RS170A timing
010:
7:5
TV_FMT
011:
PAL-B, D, G, H, I
PAL-M
100:
PAL-N (Argentina)
101:
PAL-N (non Argentina)
110-111:
reserved
4
MSTR
1 = Master Mode, 0 = Slave Mode
3
CCIR656 video input is in ITU R.BT656 format with embedded EAV and SAV (0 = off, 1 = on)
2
PROG
Progressive scanning enable (enable = 1)
1
IN_MODE Input select (0 = solid background, 1 = use V [7:0] data)
0
CBCR_UV enable YCbCr to YUV conversion (1 = enable, 0 = disable)
Control Register 1
Address
Bit Number
Bit Name
Default
0×01
CONTROL_1 Read/Write
7
6
LUM DEL
0
0
5
CH BW
0
4
LPF_ON
0
Default Value = 02h
3
2
RGB_BW
FLD
0
0
Bit
Mnemonic
Function
luma delay on the composite1 output
00:
no delay (default)
7:6
LUM DEL 01:
1 pixel clock delay
10:
2 pixel clock delay
11:
3 pixel clock delay
1
PED
1
0
CBCRSEL
0
38
DS278F6

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]