CS5368(2005) 查看數據表（PDF） - Cirrus Logic

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CS5368
(Rev.:2005)

114 dB, 192 kHz, 8-Channel A/D Converter

Cirrus Logic 

SERIAL AUDIO INTERFACE - I²S/LJ TIMING

The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS.

CS5368

Sample Rates

SCLK Frequency1

SCLK Period

SCLK Duty Cycle

LRCK setup

LRCK hold

SDOUT setup

SDOUT hold

Parameter

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

1/(64*216 kHz)

before SCLK rising

after SCLK rising

before SCLK rising

after SCLK rising

Symbol

-

-

-

-

tPERIOD

tHIGH

tSETUP1

tHOLD1

tSETUP2

tHOLD2

Min

2

54

108

-

72.3

30

20

20

10

10

Typ

-

-

-

64*Fs

-

-

-

-

-

-

Max Unit

54

kHz

108

kHz

216

kHz

-

Hz

-

ns

70

%

-

ns

-

ns

-

ns

-

ns

Notes:

1. In Master mode, the SCLK/LRCK ratio is fixed at 64. In Slave Mode, the SCLK/RCLK ratio can be set ac-

cording to preference. However, chip performance is guaranteed only when using the ratios in Section

4.6.9 Master and Slave Clock Frequencies on page 29.

SCLK

LRCK

SDOUT

tPERIOD

tHIGH

tHOLD1

channel

data

tSET UP1

channel

tSE T UP2

data

tHOLD2

Figure 2. I²S/LJ Timing

18

DS624A1

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