CS5368(2005) 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS5368 Datasheet PDF : 39 Pages
| |||
CS5368
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling1
thdd
0
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
tsud
250
trc
-
tfc
-
tsusp
4.7
tack
300
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
1000
ns
Notes:
1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL
RST
t irs
Stop
Start
SDA
S CL
t buf
t hdst
t high
t
lo w
t
hdd
t sud t ack
Figure 4. I²C Timing
Repe ated
Sta rt t rd
t hdst
Stop
t fd
t fc
t susp
t sust
t rc
20
DS624A1
Share Link: 