CS5368(2005) 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS5368 Datasheet PDF : 39 Pages
| |||
CS5368
TDM MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
÷4
49.152
24.576
512
256
÷3
36.864
24.576
384
256
DSM
÷2
24.567
24.576
256
256
Table 8. Frequencies for 96 kHz Sample Rate using TDM
÷1.5
18.384
24.576
192
256
÷1
12.288
24.576
128
256
TDM MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
÷4
49.152
49.152
256
256
÷3
36.864
49.152
192
256
QSM
÷2
24.567
49.152
128
256
Table 9. Frequencies for 192 kHz Sample Rate using TDM
÷1.5
18.384
49.152
96
256
÷1
12.288
49.152
64
256
4.7 Serial Audio Formats
The ADC supports I²S, Left-Justified and TDM digital interface formats. Audio data should be latched by the
receiver on the rising edge of SCLK within the specified setup and hold times.
SCLK
receiver latches data on rising edges of SCLK
LRCK
SDOUT
SCLK
MSB
Odd Channels 1,3, ...
...
LSB
MSB
Figure 12. LJ Format
receiver latches data on rising edges of SCLK
Even Channels 2,4, ...
...
LSB
MSB
LRCK
Odd Channels 1,3, ...
Even Channels 2,4, ...
SDOUT
MSB
...
LSB
MSB
...
LSB
MSB
Figure 13. I²S Format
FS
Bit or Word Wide
256 sclks
SCLK
TDM OUT
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 14. TDM Format
32 clks
32 clks
32 clks
30
DS624A1
Share Link: 