CS5368(2005) 查看數據表（PDF） - Cirrus Logic
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CS5368 Datasheet PDF : 39 Pages
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CS5368
5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC.
5.1 Register Quick Reference
Adr Name
00 REVI
01 GCTL
02 OVFL
03 OVFM
04
HPF
05 RESERVED
06 PDNE
07 RESERVED
08 MUTE
09 RESERVED
0A SDEN
7
6
5
4
CHIP-ID[3:0]
CP-EN CLKMODE
MDIV[1:0]
OVFL8 OVFL7 OVFL6 OVFL5
OVFM8 OVFM7 OVFM6 OVFM5
HPF8
HPF7
HPF6
HPF5
-
-
-
-
not used
PDN-BG PDN-OSC
-
-
-
-
MUTE8 MUTE7 MUTE6 MUTE5
-
-
-
-
not used
3
2
1
0
REVISION[3:0]
DIF[1:0]
MODE[1:0]
OVFL4 OVFL3 OVFL2 OVFL1
OVFM4 OVFM3 OVFM2 OVFM1
HPF4
HPF3
HPF2
HPF1
-
-
-
-
PDN87 PDN65 PDN43 PDN21
-
-
-
-
MUTE4 MUTE3 MUTE2 MUTE1
-
-
-
-
SDEN4 SDEN3 SDEN2 SDEN1
5.2 00h (REVI) Chip ID Code & Revision Register
R/W
7
6
5
4
3
2
1
0
R
CHIP-ID[3:0]
REVISION[3:0]
Default: See description
The Chip ID Code & Revision Register is used to store the ID and revision of the chip.
Bits[7:4] contain the chip ID, where the CS5368 is represented with a value of 0x8.
Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is
represented as 0x1, etc.
5.3 01h (GCTL) Global Mode Control Register
R/W
R/W
7
6
CP-EN CLKMODE
5
4
MDIV[1:0]
3
2
DIF[1:0]
1
0
MODE[1:0]
Default: 0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial
audio data format and the Master clock dividers for all channels. It also contains a control port
enable bit.
Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in
Stand-Alone Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and
the corresponding register values become functional.
DS624A1
35
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