CS61583 查看數據表（PDF） - Cirrus Logic

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CS61583

Dual T1/E1 Line Interface

Cirrus Logic 

CS61583

Power Supplies

AGND1, AGND2 : Analog Ground (PLCC pins 31, 33; TQFP pins 21, 23)

Analog supply ground pins.

AV+ : Analog Power Supply (PLCC pin 34; TQFP pin 24)

Analog supply pin for the internal bandgap reference and timing generation circuits.

BGREF : Bandgap Reference (PLCC pin 32; TQFP pin 22)

This pin is used by the internal bandgap reference and must be connected to ground

by a 4.99kΩ ±1% resistor to provide an internal current reference.

DGND1, DGND2, DGND3 : Digital Ground (PLCC pins 1, 18, 67; TQFP pins 57, 9, 55)

Power supply ground pins for the digital circuitry of both channels.

DV+ : Power Supply (PLCC pin 68; TQFP pin 56)

Power supply pin for the digital circuitry of both channels.

RGND1, RGND2 : Receiver Ground (PLCC pins 30, 39; TQFP pins 20, 29)

Power supply ground pins for the receiver circuitry.

RV+1, RV+2 : Receiver Power Supply (PLCC pins 29, 40; TQFP pins 19, 30)

Power supply pins for the analog receiver circuitry.

TGND1, TGND2 : Transmit Ground (PLCC pins 22, 47; TQFP pins 13, 36)

Power supply ground pins for the transmitter circuitry.

TV+1, TV+2 : Transmit Power Supply (PLCC pins 21, 48; TQFP pins 12, 37)

Power supply pins for the analog transmitter circuitry.

T1/E1 Data

RCLK1, RCLK2 : Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)

RPOS1, RPOS2 : Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47)

RNEG1, RNEG2 : Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46)

The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these

pins. The CLKE pin determines the clock edge on which RPOS and RNEG are stable and

valid. A positive pulse (with respect to ground) received on RTIP generates a logic 1 on RPOS,

and a positive pulse received on RRING generates a logic 1 on RNEG.

RDATA1, RDATA2 : Receive Data (PLCC pins 11, 58; TQFP pins 2, 47)

In coder mode (CODER = 1), the decoded digital data stream from RTIP and RRING is output

on RDATA in NRZ format. The CLKE pin determines the clock edge on which RDATA is

stable and valid.

RTIP1, RTIP2 : Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32)

RRING1, RRING2 : Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31)

The receive AMI signal from the line interface is input on these pins. The recovered clock and

data are output on RCLK, RPOS, and RNEG (or RDATA).

DS172PP5

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