CS61583 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS61583

Dual T1/E1 Line Interface

Cirrus Logic 

APPLICATIONS

CS61583

CLKE ATTEN2 AMI1 CON11 TAOS1 RLOOP1 AMI2 CON12 TAOS2 RLOOP2

REFCLK 1XCLK RESET ATTEN1 CODER1 CON01 CON21 LLOOP1 CODER2 CON02 CON22 LLOOP2

Clock Generator

TCLK1

Hardware Control

T1 1:1.15

TTIP1 0.47µFC1

transmit

Framer

TPOS1 (TDATA1)

TNEG1 (AIS1)

RCLK1

Channel 1

TRING1

R1

T2 1:1.15

RTIP1 0.47µF

RPOS1 (RDATA1)

receive

RNEG1 (BPV1)

Framer

TCLK2

TPOS2 (TDATA2)

TNEG2 (AIS2)

RCLK2

Channel 2

RRING1

R2

T3 1:1.15

TTIP2 0.47µFC2

transmit

TRING2

R3

T4 1:1.15

RTIP2

0.47µF

RPOS2 (RDATA2)

receive

RNEG2 (BPV2)

Power Supply

RRING2

R4

AV+ AGND1:2 BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3

0.1 µF 2

VCC

+

1 µF

R3

4.99kΩ 0.1 µF

0.1 µF

+

22 µF

0.1 µF

0.1 µF

3

0.01 µF

Figure A1. Typical Connection Diagram

Data Rate (MHz)

1.544

2.048

REFCLK Frequency (MHz)

1XCLK = 1

1XCLK = 0

1.544

12.352

2.048

16.384

Cable (Ω)

100

75

120

Table A1. CS61583 External Components

R1-R4 (Ω)

38.3

28.7

45.3

C1-C2 (pF)

220

470

220

Line Interface

Figure A1 illustrates a typical connection diagram

and Table A1 lists the external components that

are required in T1 and E1 applications.

In the transmit line interface circuitry, capacitors

C1 and C2 provide transmitter return loss. The

0.47 µF capacitor in series with the transformer

primary prevents output stage imbalances from

producing a DC current through the transformer

that might saturate the transformer and result in

an output level offset.

DS172PP5

In the receive line interface circuitry, resistors R1-

R4 provide receive impedance matching and

receiver return loss. The 0.47 µF capacitor to

ground provides the necessary differential input

voltage reference for the receiver.

Power Supply

As shown in Figure A1, the CS61583 operates

from a 5.0 Volt supply. Separate analog and digi-

tal power supply and ground pins provide internal

isolation. The TGND, RGND, and DGND ground

pins must not be more negative than AGND. It is

recommended that all of the supply pins be con-

nected together at the device. A 4.99kΩ ±1%

31

Share Link: