CS8900A
Crystal LAN™ Ethernet Controller
Not in Boundary Scan
Test Mode
TEST switches low (AEN m ust be low)
ENTER BOUNDARY SCAN:
C S8900A resets, all digital
output pins and bi-directional
pins enter H igh-Z state,
and AEN becom es shift clock
AEN switches high
OUTPUT CYCLE
AEN switches low
34 cycles
AEN switches high
Selected output
goes low
INPUT CYCLE
AEN switches low
50 cycles
AEN switches high
AEN switches low
AEN switches high
All digital output pins and
bi-directional pins enters
High-Z state
TEST switches hig h
EXIT BOUNDARY SCAN:
AEN becomes ISA bus
Address Enable
Figure 32. Boundary Scan Continuity Cycle
Selected input
copied out
to the
EE D ataO ut
pin
CIRRUS LOGIC PRODUCT DATASHEET
110
DS271F4