CS8900A
Crystal LAN™ Ethernet Controller
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol Min
10BASE-T Receive
Allowable Received Jitter at Bit Cell Center
Allowable Received Jitter at Bit Cell Boundary
Carrier Sense Assertion Delay
Invalid Preamble Bits after Assertion of Carrier Sense
Carrier Sense Deassertion Delay
10BASE-T Link Integrity
tTRX1
-
tTRX2
-
tTRX3
-
tTRX4
1
tTRX5
-
First Transmitted Link Pulse after Last Transmitted Packet
tLN1
8
Time Between Transmitted Link Pulses
tLN2
8
Width of Transmitted Link Pulses
tLN3
60
Minimum Received Link Pulse Separation
tLN4
2
Maximum Received Link Pulse Separation
tLN5
25
Last Receive Activity to Link Fail (Link Loss Timer)
tLN6
50
Typ
Max Unit
-
±13.5 ns
-
±13.5 ns
540
-
ns
-
2
bits
270
-
ns
16
24
ms
16
24
ms
100
200
ns
-
7
ms
-
150 ms
-
150 ms
RXD±
tTR X 1
tT R X 3
tT R X 4
tT R X 2
C arrier Sense (internal)
Figure 42. 10BASE-T Receive
TXD±
RXD±
L IN K L E D
t LN1
tLN2
tLN3
tLN6
tLN4
tLN5
Figure 43. 10BASE-T Link Integrity
tTR X5
CIRRUS LOGIC PRODUCT DATASHEET
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DS271F4