DD28F032SA 查看數據表（PDF） - Intel

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DD28F032SA

32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile™ MEMORY

Intel 

DD28F032SA

E

DEEP

POWER-DOWN

VIH

ADDRESSES (A)

NOTE 1 V IL

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

t AVAV

V IH

ADDRESSES (A)

NOTE 2 V IL

t AVAV

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

WRITE READ EXTENDED

REGISTER COMMAND

AIN

t AVEH

A IN

t AVEH

t EHAX

t EHAX

NOTE 3

V IH

WE# (W)

V IL

V IH

OE# (G) V IL

t WLEL

t EHWH

t EHGL

READ EXTENDED

STATUS REGISTER DATA

A=RA

READ COMPATIBLE

STATUS REGISTER DATA

CEx#(E) V IH

t EHEL

t EHQV1,2

NOTE 4 V IL

t ELEH

t DVEH

t EHDX

V IH

HIGH Z

DATA (D/Q)

V IL

t PHEL

D IN

D IN

D IN

t GHEL

D OUT

D IN

V OH

RY/BY# (R)

V OL

t EHRL

V IH

RP# (P)

V IL

t RHPL

NOTE 5

VPPH

t VPEH

t QVVL

VPP (V)

VPPL

V IH

V IL

0490_15

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. For 28F016SA No. 1:CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.

5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.

Figure 15. Alternate AC Waveforms for Command Write Operations

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