LTC1096AI(RevB) 查看數據表（PDF） - Linear Technology

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LTC1096AI
(Rev.:RevB)

Micropower Sampling 8-Bit Serial I/O A/D Converters

Linear Technology 

LTC1096/LTC1096L

LTC1098/LTC1098L

APPLICATI S I FOR ATIO

Power Down and Wake-Up Time

The LTC1096(L)/LTC1098(L) draw power when the CS pin

is low and shut themselves down when that pin is high. In

order to have a correct conversion result, a 10µs wake-up

time must be provided from CS falling to the first falling

clock (CLK) after the first rising CLK for the LTC1096(L)

and from CS falling to the MSBF bit CLK falling for the

LTC1098(L) (see Operating Sequence). If the LTC1096(L)/

LTC1098(L) are running with clock frequency less than or

equal to 100kHz, the wake-up time is inherently provided.

Example

Two cases are shown at right to illustrate the relationship

among wake-up time, setup time and CLK frequency for

the LT1096(L).

In Case 1 the clock frequency is 100kHz. One clock cycle

is 10µs which can be the wake-up time, while half of that

can be the setup time. In Case 2 the clock frequency is

50kHz, half of the clock cycle plus the setup time (=1µs)

can be the wake-up time. If the CLK frequency is higher

tWAKEUP

CS

tsu

CLK

DOUT

NULL BIT

B7

Case 1. Timing Diagram

tWAKEUP

CS

CLK

DOUT

tsu

10µs

Case 2. Timing Diagram

LTC1096/98 • AI Ex.

than 100kHz, Figure 1 shows the relationship between the

wake-up time and setup time.

The wake-up time is inherently provided for the LTC1098(L)

with setup time = 1µs (see Figure 2).

tCYC

CS

CLK

DOUT

tsuCS

tWAKEUP

HI-Z

POWER

DOWN

NULL

BIT

Hi-Z

B7 B6 B5 B4 B3 B2 B1 B0

(MSB)

tCONV

tCYC

CS

CLK

DOUT

tsuCS

tWAKEUP

Hi-Z

POWER

DOWN

NULL

BIT

B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7*

(MSB)

tCONV

Hi-Z

LTC1096/98 F01

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

Figure 1. LTC1096(L) Operating Sequence

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