LTM2883 查看數據表（PDF） - Linear Technology

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LTM2883

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power

Linear Technology 

LTM2883

Applications Information

Maximum data rate for single direction communication,

master to slave, is 8MHz, limited by the systems encod-

ing/decoding scheme or propagation delay. Timing details

for both variations of clock phase are shown in Figures 8

and 9 and Table 4.

Additional requirements to insure maximum data rate

are:

• CS is transmitted prior to (asynchronous) or within the

same (synchronous) data packet as SDI

• SDI and SCK set-up data transition occur within the

same data packet. Referencing Figure 6, SDI can pre-

cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns

(t8 → t9) and not violate this requirement. Similarly in

Figure 8, SDI can precede SCK by up to 13ns (t4 → t5)

or lag SCK by 3ns (t5 → t6).

Inter-IC Communication (I2C) Bus

The LTM2883-I provides an I2C compatible isolated inter-

face, Clock (SCL) is unidirectional, supporting master mode

only, and data (SDA) is bidirectional. The maximum data

CPHA = 0

CS = SDOE

CS2

SDI

SDI2

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)

t0

t1 t2

t3 t4 t5

t7

t6

t8

t9

Figure 8. SPI Timing, Unidirectional, CPHA = 0

t11 t12

2883 F08

CPHA = 1

CS = SDOE

CS2

SDI

SDI2

SCK (CPOL = 0)

SCK2 (CPOL = 0)

SCK (CPOL = 1)

SCK2 (CPOL = 1)

20

t0

t1 t2

t3 t4 t5

t7

t6

t8

t9

t10 t11 t12

2883 F09

Figure 9. SPI Timing, Unidirectional, CPHA = 1

2883f

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